The present invention relates to focal plane array configurations in general, and more particularly, to a flip-chip focal plane array structure and method of batch-fabricating a plurality of the same in which precision alignment of the interconnection contacts between an infrared radiation detector integrated circuit and a signal processor integrated circuit of the focal plane array is avoided.
Generally, it is desired to fabricate the infrared radiation detector integrated circuit and the signal processor integrated circuit of a focal plane array configuration separately. The infrared radiation detector integrated circuit of the focal plane array generally comprises a substrate wafer of a material composition which provides the properties of being sensitive to a predetermined wavelength window of infrared radiation. One side of the substrate may be doped appropriately for infrared radiation impingement thereon, the doped surface region generally being anti-reflective to the infrared radiation. The other side of the infrared radiation detector wafer usually has an array of regions doped with impurities, each being covered with a metallic contact. Each contact of the infrared detector array may provide an electrical signal representative of a picture element or pixel of the IR image which impinges the surface area of the one side thereof. Presently, infrared detectors of this type have arrays on the order of 16.times.32 or 32.times.32 pixels, but much larger arrays are being proposed.
The other integrated circuit of the focal plane array configuration is generally a signal processing microelectronic circuit, like a charge coupled device (CCD), for example. Each cell of the array of the charge coupled device is geometrically aligned to be in a 1 to 1 dimensional correspondence with each picture element contact of the infrared detector integrated circuit array and metallic contacts are formed at injection input points of each of the charge coupled device cells.
In connecting the two integrated circuits together to form the focal plane array configuration, each pixel contact of the infrared detector is coupled correspondingly to each cell of the signal processor chip. Accordingly, the two integrated circuits are connected together on an element-to-element basis with well-known metal bonding techniques, the operation being commonly referred to as a flip-chip fabrication method. For an example of such a flip-chip configuration, reference is herein made to the U.S. issued U.S. Pat. No. 4,067,104, issued to John M. Tracey on Jan. 10, 1978 and entitled, "Method of Fabricating an Array of Flexible Metallic Interconnects for Coupling Microelectronics Components".
It is clearly evident that prior to these 1 to 1 metal bonding operations of the flip-chip focal plane arrays, some precision registration step must be implemented. In some cases, "see through" (infrared or X-ray) or front-to-back surface reflection alignment techniques are relied upon to achieve the precise registry required between the large number of array contacts of the detector and signal processor on a 1 to 1 basis. At the very high detector array densities and fine geometries being proposed for utilization in focal plane array technology, it is understood that the precision alignment step is likely to become a difficult and time-consuming task which appears incompatible with the high volume and low cost benefits of modern semiconductor fabrication technology.
Consequently, it appears that a process-compatible interconnect bonding technology should be adopted for achieving parallel interconnection of many thousands of electrical connections simultaneously in one operation in connection with bonding the arrays of the microelectronic infrared detector and signal processing chips of an infrared focal plane array configuration. The technology should, of course, avoid the need for high precision alignment of the infrared detector and signal processing arrays.